Integrated GPU Cache Coherence on Orin

Issue Overview

The discussion revolves around the confusion regarding the bidirectional cache coherence between the CPU and integrated GPU (iGPU) on the Nvidia Jetson Orin Nano Dev board. Users are experiencing uncertainty about whether the Orin architecture allows for effective communication and cache sharing between these components, particularly concerning pinned memory.

Symptoms and Context:

• Users are questioning if the iGPU on the Orin supports bidirectional cache coherence or if it only allows for one-way communication where the GPU can read from the CPU cache.
• The issue arises during discussions about performance testing and memory management, particularly when using CUDA and pinned memory.
• Conflicting documentation has led to confusion, with some users referencing older architectures that do not support this feature.
• The problem seems to be prevalent among developers working with CUDA for Tegra, particularly those transitioning from previous Jetson models.

Hardware and Software Specifications:

• The Jetson Orin Nano features a GPU architecture of sm_87, which is a significant upgrade from previous models like sm_53.