Orin Nano Quiescent Power Consumption in Low Power State

Issue Overview

The Nvidia Jetson Orin Nano Development Board users are seeking information about the quiescent power consumption when the board is in a low power state. Specifically, they are interested in the current draw on the VDD (Voltage Drain Drain) line when the POWER_EN (Power Enable) signal is low. This information is crucial for designing carrier boards that aim to achieve very low power consumption in sleep states.

The issue arises in the context of power management design for custom carrier boards. Users are considering having a low-power microcontroller (MCU) control the POWER_EN signal while keeping VDD constantly powered by a 5V source. This approach is intended to follow the design guide for proper power-up and power-down sequencing.

Possible Causes

1. Hardware Design Constraints: The Orin Nano module may have certain components that require a minimum amount of power even in the off state, leading to a non-zero quiescent current.

2. Power Management Architecture: The specific power management architecture of the Orin Nano might not allow for complete power cutoff without violating the recommended power sequencing guidelines.

3. Component Characteristics: Various devices attached to the VDD_IN line may have their own quiescent current requirements, contributing to the overall power consumption in the low power state.

4. Design Trade-offs: The balance between maintaining certain functionalities (like quick wake-up capabilities) and achieving ultra-low power consumption may result in a higher quiescent current than desired for some applications.

Troubleshooting Steps, Solutions & Fixes

1. Understand the Quiescent Current Range:

   • The power-off current (quiescent current) of the Orin Nano module when POWER_EN is low is approximately 600µA to 1mA.
   • This range accounts for the variability in quiescent current of all devices attached to VDD_IN.

2. Evaluate Power Budget:

   • Assess whether the quiescent current range (600µA – 1mA) is acceptable for your specific application’s low power requirements.
   • If not, consider alternative power management strategies.

3. Explore Alternative Power Management Strategies:

   • If the quiescent current is too high for your application, consider implementing a power cutoff mechanism for VDD using a load switch or similar component.
   • Be aware that this approach may deviate from the recommended power sequencing guidelines and could introduce other challenges.

4. Consult Nvidia Documentation:

   • Review the Jetson Orin Nano Developer Kit User Guide for detailed information on power management and sequencing.
   • Check for any application notes or technical bulletins that might provide additional insights on low-power design considerations.

5. Consider System-Level Power Optimization:

   • Evaluate other components in your system that might contribute to overall power consumption.
   • Implement aggressive power-saving techniques in your software to minimize active time and maximize time spent in low-power states.

6. Seek Engineering Support:

   • If your application requires even lower power consumption, consider reaching out to Nvidia’s engineering support for guidance on advanced power management techniques or potential future product enhancements.

It’s worth pointing out that according to the forum discussion, there is currently no way to reduce the quiescent current below the specified range for the Orin Nano module while maintaining the recommended power sequencing. Designers should carefully consider this limitation when developing ultra-low power applications using this platform.