Power-Up Sequence Discrepancy in Nvidia Jetson Orin Nano Design Guide

Issue Overview

The Nvidia Jetson Orin Nano Design Guide contains a discrepancy regarding the power-up sequence. Specifically, Figure 6-3 in the guide shows a 400 ms delay between VDD_IN and POWER_EN. However, this delay is not mentioned elsewhere in the document, causing confusion among developers and hardware designers. Users are questioning the necessity of this delay and its implications for their designs.

Possible Causes

1. Documentation Error: The 400 ms delay might be an outdated specification that was mistakenly included in the design guide.

2. Hardware Differences: The delay could be related to different Power Management Integrated Circuits (PMICs) used in various Jetson models.

3. Legacy Compatibility: The delay might have been included to maintain compatibility with older Jetson models, such as the Jetson Nano.

4. Transitional Design Phase: The documentation may be in a transitional phase, reflecting both current and future design requirements.

Troubleshooting Steps, Solutions & Fixes

1. Clarification on Delay Requirement:

   • The 400 ms delay is not required for the Jetson Orin Nano series.
   • This delay is only applicable to the Jetson Nano, not the Orin NX/Nano models.

2. Design Considerations:

   • When designing hardware for the Jetson Orin Nano, you do not need to implement the 400 ms delay between VDD_IN and POWER_EN.
   • Focus on the power-up sequence specifications that are consistently mentioned throughout the Design Guide, excluding the 400 ms delay.

3. Documentation Updates:

   • Nvidia has acknowledged the issue and plans to update the related documentation.
   • Future releases of the Design Guide will remove the 400 ms delay specification.

4. Best Practices:

   • Always refer to the latest version of the Jetson Orin Nano Design Guide for the most up-to-date information.
   • If in doubt about specific hardware requirements, consult Nvidia’s official support channels or forums for clarification.

5. Compatibility Considerations:

   • If designing hardware that needs to be compatible with both Jetson Nano and Orin Nano, consider implementing a configurable delay:

     // Example: Configurable delay in Verilog
     module power_sequence (
         input clk,
         input reset,
         input is_jetson_nano,
         input vdd_in,
         output reg power_en
     );
     
     reg [9:0] counter;
     
     always @(posedge clk or posedge reset) begin
         if (reset) begin
             counter <= 0;
             power_en <= 0;
         end else if (vdd_in) begin
             if (is_jetson_nano && counter < 400) begin
                 counter <= counter + 1;
             end else begin
                 power_en <= 1;
             end
         end
     end
     
     endmodule
     

6. Monitoring Future Updates:

   • Keep an eye on Nvidia’s official documentation and release notes for any changes related to the power-up sequence.
   • Consider subscribing to Nvidia’s developer newsletters or following their official channels for timely updates on documentation changes.

By following these guidelines and staying informed about the latest documentation updates, developers can ensure proper implementation of the power-up sequence for the Nvidia Jetson Orin Nano, avoiding potential issues related to the outdated 400 ms delay specification.