Jetson Orin Nano: Bootloader Verification and Memory Testing

Issue Overview

Users have raised questions regarding the bootloader functionality and memory testing capabilities of the Nvidia Jetson Orin Nano development board. Specifically, they are interested in understanding how the bootloader verifies the integrity of the kernel and device tree during the boot process, and whether built-in self-tests (BIST) are performed on the bootloader to detect DDR memory defects.

Possible Causes

The inquiries stem from the need to ensure the reliability and stability of the Jetson Orin Nano during the boot process. Potential reasons for these questions include:

  1. Ensuring proper loading of the kernel and device tree: Users want to prevent the system from booting with corrupted or incorrect data, which could lead to system instability or failure.

  2. Detecting DDR memory defects: Identifying memory issues early in the boot process can prevent system crashes or data corruption caused by faulty memory modules.

  3. Exploring alternative verification methods: Users are interested in simpler ways to verify the kernel and device tree integrity, as an alternative to the secure boot feature.

  4. Utilizing watchdog timers: Investigating the possibility of using watchdog timers to automatically reset and reboot the system if the kernel fails to boot properly.

Troubleshooting Steps, Solutions & Fixes

  1. Secure Boot and Encryption:

  2. DRAM Memory Tests:

    • UEFI support for DRAM memory tests will be available in the next release (Jetpack 5.1.3, scheduled for December).
    • The memory test logic can be found in the following header file: MemoryVerificationLib.h
    • The implementation of the memory tests is located in: MemoryVerificationLib.c
    • The memory tests are called from the platform boot manager: PlatformBm.c#L213
    • Several test modes are available; refer to the source code for specific use cases.
  3. Non-Secure Default Boot:

    • The UEFI non-secure default boot does not verify the kernel image and DTB; it loads them directly.
    • If a simpler verification method is required, consider using U-Boot’s mkimage header CRC verification (dcrc, hcrc) as an alternative.
  4. Watchdog Timer:

    • The watchdog timer is enabled by default in the Linux kernel on the Jetson Orin Nano.
    • It can be observed in the serial console log, with messages like:
      [    1.539326] tegra_wdt_t18x 2190000.watchdog: Tegra WDT init timeout = 120 sec
      [    1.546478] tegra_wdt_t18x 2190000.watchdog: Registered successfully
      
    • The watchdog timer is started immediately after the Linux kernel is booted, not in UEFI.
    • If the kernel panic occurs and the system is stuck for longer than 120 seconds, the watchdog timer will trigger a reset to help exit that state.

Note: For specific use cases related to DDR memory testing during mass production, consult with Nvidia’s technical support team for detailed information on the testing methodology and logic.

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