Enabling extperiph1/2 output

Issue Overview

The issue discussed in the forum revolves around enabling clock outputs for the Nvidia Jetson Orin Nano Developer Kit, specifically for pins designated as CAM0_MCLK (EXTPERIPH1_CLK) and CAM1_MCLK (EXTPERIPH2_CLK). Users reported that despite attempting to set the clock rates using the debugfs interface, they observed no signal output on the respective pins. The context of the problem occurs during setup, with users utilizing L4T version 35.4.1 on a custom carrier board. The symptoms include:

• No signal detected on the output pins when probed.
• Errors encountered when attempting to retrieve clock information via the kernel API (specifically an invalid pointer error code -2).
• Consistent failure to see any clock output despite following expected procedures.

This issue significantly impacts user experience by preventing validation of target frequencies and waveform checks, which are critical for applications such as dual camera configurations.

Possible Causes

Several potential causes for the issue have been identified:

• Hardware Incompatibilities or Defects: The custom carrier board may not be correctly configured or compatible with the Jetson Orin Nano module.

• Software Bugs or Conflicts: There might be unresolved bugs in the L4T version being used, affecting clock management functionalities.

• Configuration Errors: Incorrect device tree entries or pinmux settings could lead to improper clock signal routing.

• Driver Issues: The kernel drivers responsible for handling clock outputs might not be functioning as intended.

• Environmental Factors: External factors such as power supply inconsistencies could affect signal integrity.

• User Errors or Misconfigurations: Users may not have correctly followed procedures for enabling clocks or configuring their systems.

Troubleshooting Steps, Solutions & Fixes

To address this issue effectively, users can follow these comprehensive troubleshooting steps:

1. Verify Hardware Connections:

   • Ensure that all connections to the custom carrier board are secure and correctly configured according to the Jetson Orin NX Series Design Guide.

2. Check Device Tree Configuration:

   • Update your device tree entries to include necessary clock definitions:

     clocks = <&bpmp_clks TEGRA234_CLK_EXTPERIPH1>, <&bpmp_clks TEGRA234_CLK_PLLP_OUT0>;
     clock-names = "mclk", "parent";
     

3. Utilize Kernel API Correctly:

   • Use the following code snippet to get clocks:

     struct clk* mclk = devm_clk_get(dev, "mclk");
     struct clk* pclk = devm_clk_get(dev, "parent");
     clk_prepare(mclk);
     clk_set_parent(mclk, pclk);
     clk_set_rate(mclk, 37125000);
     clk_enable(mclk);
     

   • Ensure error checking is implemented to catch any issues during this process.

4. Debugfs Interface Usage:

   • Confirm that you are using the debugfs interface correctly. Set up clocks in this sequence:

     echo 3187500 > /sys/kernel/debug/bpmp/debug/clk/extperiph1/rate
     echo 1 > /sys/kernel/debug/bpmp/debug/clk/extperiph1/state
     

5. Pinmux Settings:

   • Review and update pinmux settings if necessary. Check if pinmux configurations are conflicting with other functionalities.

6. Testing with Different Configurations:

   • If possible, test with a known working configuration or evaluate using different pins (e.g., extperiph3 and extperiph4) as suggested in forum replies.

7. Refer to Documentation:

   • Consult relevant Nvidia documentation such as the Jetson Linux Developer Guide and specific design guides for detailed hardware configurations and software implementations.

8. Community Engagement:

   • Engage with community forums for additional insights and share findings that may assist others facing similar issues.

9. Firmware and Driver Updates:

   • Ensure that all firmware and drivers are up-to-date, as updates may resolve existing bugs affecting clock functionality.

10. Best Practices for Future Prevention:

    • Regularly check for updates to both hardware schematics and software libraries.
    • Maintain a backup of working configurations to facilitate quick recovery from future issues.

By following these steps, users can systematically diagnose and potentially resolve issues related to enabling clock outputs on their Nvidia Jetson Orin Nano Developer Kit.