Maintaining Carrier Board Power During Jetson Orin Nano System Reset

Issue Overview

Users developing custom carrier boards for the Nvidia Jetson Orin Nano are encountering challenges when attempting to implement system reset functionality. The primary concern is the ability to reset the Jetson Orin Nano module without powering down the carrier board’s voltage supplies. This issue arises from the desire to maintain power to certain components on the carrier board during a reset operation, which conflicts with the standard design guidelines for the Jetson platform.

Possible Causes

1. Misunderstanding of Design Guidelines: Developers may be attempting to deviate from Nvidia’s recommended design practices, specifically regarding the use of the SYS_RESET* signal to control power enables for voltage regulators on the carrier board.

2. Incomplete Knowledge of Reset Types: There may be confusion about the differences between cold resets and warm resets, and their respective impacts on power sequencing.

3. Timing Constraints: Concerns about the ability of carrier board supplies to fully power down within the short duration of a system reset signal (approximately 50ms) may be leading to alternative design considerations.

4. I/O Pin State Concerns: Uncertainty about the criticality of I/O pin states during a warm system reset might be influencing design decisions.

Troubleshooting Steps, Solutions & Fixes

Understanding Reset Types and Their Implications

1. Cold Reset vs. Warm Reset:

   • A cold reset involves a complete power cycle of the entire system.
   • A warm reset only resets the SoC and QSPI boot device, without affecting the PMIC on the module or the module’s I/O power status.

2. Warm Reset Behavior:

   • During a warm reset triggered by an external signal pulling SYS_RST* low, the Power_EN signal from the Jetson Orin Nano Dev Kit remains high.
   • This behavior allows carrier board power rails to remain on during a warm reset.

Adhering to Design Guidelines

1. Follow Nvidia’s Design Guide:

   • It is strongly recommended to control carrier power rails using the RESET signal, as per Nvidia’s design guidelines.
   • Deviating from these guidelines may lead to unpredictable behavior or potential damage to the system.

2. Power Sequencing:

   • Implement proper power sequencing as outlined in the Jetson Orin Nano Developer Guide.
   • Ensure that your carrier board design can handle both cold and warm reset scenarios correctly.

Addressing Timing Concerns

1. Reset Hold Time:

   • The SYS_RST* hold time of approximately 50ms may not be sufficient for carrier board supplies to fully power down.
   • For warm resets, this is not a concern as the carrier board supplies can remain powered.

2. Power Sequencing Timing:

   • Request and review power sequence timing diagrams for warm resets from Nvidia support if needed for your specific implementation.

Handling I/O Pin States

1. I/O Pin Behavior During Warm Reset:

   • During a warm reset, the module’s I/O power status is not affected.
   • This means that I/O pins should maintain their state during a warm reset, alleviating concerns about pins being pulled high unexpectedly.

2. Design Considerations:

   • Ensure that your carrier board design can handle potential I/O state changes during cold resets.
   • Implement appropriate pull-up or pull-down resistors on critical I/O lines to define safe states during power transitions.

Implementing a Custom Reset Solution

If maintaining carrier board power during all types of resets is crucial for your application:

1. Use Warm Reset Functionality:

   • Leverage the warm reset feature when possible, as it allows carrier board power to remain on.

2. Implement a Custom Reset Controller:

   • Design a microcontroller-based reset management system on your carrier board.
   • This controller can manage the reset sequence, ensuring carrier board supplies remain powered while still properly resetting the Jetson module.

3. Power Isolation:

   • Implement power domain isolation between the Jetson module and carrier board components that need to remain powered.
   • Use level shifters or isolators to manage signal integrity between power domains.

Best Practices

1. Thorough Testing:

   • Conduct extensive testing of your reset implementation under various conditions.
   • Verify system stability and proper functionality after both warm and cold resets.

2. Documentation:

   • Maintain detailed documentation of your custom reset implementation, including any deviations from Nvidia’s design guidelines.
   • Document the reasons for these deviations and any potential risks or limitations.

3. Thermal Considerations:

   • Ensure that maintaining power to carrier board components during resets does not lead to thermal issues or excessive power consumption.

4. Fail-Safe Mechanisms:

   • Implement watchdog timers or other fail-safe mechanisms to force a full system reset if the custom reset solution encounters issues.

By following these guidelines and implementing appropriate solutions, developers can create carrier boards for the Jetson Orin Nano that meet their specific reset requirements while maintaining system integrity and reliability.