When does the Orin Nano I/O pins enter POR state?

Issue Overview

Users of the Nvidia Jetson Orin Nano Dev board have raised questions regarding the Power-On Reset (POR) state of the I/O pins as indicated in the "Jetson Orin NX Series and Orin Nano Series Pinmux Config Template." Specifically, users are seeking clarity on what constitutes a power-on reset that would reset the I/O pins to their default values as specified in the pin mux configuration.

Symptoms and Context

• Users are unsure if specific actions, such as powering up the Orin Nano module or manipulating signals on the carrier board, will trigger a reset of the I/O pins.
• The issue arises during discussions about power management and pin configuration, particularly in relation to cold-boot and warm-boot scenarios.
• Relevant hardware includes the Jetson Orin Nano module and its associated carrier board.
• The frequency of this inquiry suggests that it is a common point of confusion among users.

Impact on User Experience

Uncertainty regarding the POR state can lead to misconfigurations in hardware setups, potentially causing malfunctioning applications or unexpected behavior in projects relying on precise pin states. This can hinder development efforts and lead to wasted time troubleshooting issues that stem from incorrect assumptions about pin behavior.

Possible Causes

• Hardware Incompatibilities or Defects: If there are discrepancies between the Jetson Orin Nano module and its carrier board, it may lead to unexpected behavior during power cycling.

• Software Bugs or Conflicts: Issues in the firmware or software managing I/O operations could misinterpret pin states during boot processes.

• Configuration Errors: Incorrectly configured pinmux settings may not reflect the intended behavior during power-on resets.

• Driver Issues: Outdated or incompatible drivers could affect how the hardware interacts with software, leading to improper handling of I/O states.

• Environmental Factors: Power supply inconsistencies or temperature variations could influence hardware performance during resets.

• User Errors or Misconfigurations: Misunderstanding of how power management features work can result in incorrect assumptions about when pins will reset.

Troubleshooting Steps, Solutions & Fixes

Step-by-Step Instructions

1. Verify Pinmux Configuration:

   • Ensure that the pinmux settings are correctly configured according to your project requirements.

2. Check Power Supply:

   • Confirm that your power supply is stable and meets the specifications required by the Jetson Orin Nano module.

3. Test Power Cycling Scenarios:

   • Conduct tests for each scenario mentioned:
     • Orin Nano Module Power Up: Observe if I/O pins reset according to specified POR values.
     • POWER_EN Driven Low from Carrier Board: Check if this action results in a reset of I/O states.
     • SYS_RESET Driven Low from Carrier Board*: Verify if this triggers a reset as expected.

4. Gather System Information:

   • Use terminal commands to gather logs and system information:

     dmesg | grep -i "pin"
     

   • This command helps identify any errors related to pin configurations during boot.

5. Consult Documentation:

   • Refer to the Technical Reference Manual (TRM) Section 8.4.2.2 for detailed information on power-on resets and pin states.

6. Update Drivers and Firmware:

   • Ensure that you are using the latest drivers and firmware for your Jetson Orin Nano module to avoid known issues.

Recommended Fixes

• If issues persist after testing, consider resetting your configuration by restoring factory settings and reapplying your custom configurations step-by-step.

• Engage with Nvidia’s developer forums for updates on known bugs or patches related to I/O pin behavior.

Best Practices for Prevention

• Regularly check for updates from Nvidia regarding firmware and driver releases.

• Maintain clear documentation of your configurations and any changes made to hardware setups.

Unresolved Aspects

While users have confirmed that certain actions do indeed belong to warm/cold boot categories, further clarification from Nvidia regarding specific conditions triggering POR states would be beneficial. Continued monitoring of community discussions may yield additional insights or solutions.