SYS_RESET Pin Functionality and Power Sequencing on Jetson Orin Nano

Issue Overview

The Jetson Orin Nano development board features a SYS_RESET* pin with bidirectional functionality, causing confusion among users designing carrier boards. The main concerns revolve around:

• When and how to use the SYS_RESET* pin as an input or output
• Proper implementation of the pin’s input and output characteristics in carrier board design
• Understanding which peripherals on the carrier board should be powered after the core board

These issues are crucial for developers working on custom carrier boards for the Jetson Orin Nano, as improper implementation could lead to system instability or power sequencing problems.

Possible Causes

1. Lack of documentation: Users may not have access to or be aware of the Orin Nano Design Guide, which contains essential information about the SYS_RESET* pin functionality.

2. Misunderstanding of power sequencing: Confusion about when and how the SYS_RESET* pin is controlled during power-on and power-off sequences.

3. Incorrect carrier board design: Improper implementation of the SYS_RESET* pin in custom carrier boards, potentially leading to reset or power-related issues.

4. Inadequate knowledge of peripheral power requirements: Uncertainty about which peripherals on the carrier board should be powered after the core board, potentially causing power sequencing problems.

Troubleshooting Steps, Solutions & Fixes

1. Consult the Orin Nano Design Guide:

   • Access the Orin Nano Design Guide document in the NVIDIA Developer Download Center (DLC).
   • Locate the section describing the SYS_RESET* pin functionality.

2. Understanding SYS_RESET pin functionality*:

   • The SYS_RESET* pin is bidirectional.
   • During power-on and power-off, it is controlled by the Power Sequencer or PMIC.
   • When the system is powered on, it can be driven by the carrier board to reset the SoC and QSPI boot device.

3. Implementing SYS_RESET in carrier board design*:

   • Design the carrier board to allow both input and output functionality for the SYS_RESET* pin.
   • Ensure that driving the pin from the carrier board will reset the SoC and QSPI boot device without causing a full system power cycle.

4. Power sequencing considerations:

   • Note that SYS_RESET* is not asserted externally during the power-down sequence.
   • When POWER_EN is de-asserted, the Power Sequencer or PMIC performs a power-down sequence, which includes asserting SYS_RESET*.

5. Peripheral power sequencing:

   • While specific information about peripheral power sequencing is not provided in the given discussion, it’s generally recommended to power on peripherals after the core board has stabilized.
   • Consult the Orin Nano Design Guide for detailed information on power sequencing requirements for various peripherals.

6. Best practices for carrier board design:

   • Implement proper level shifting and protection circuits for the SYS_RESET* pin if necessary.
   • Ensure that the carrier board’s power sequencing aligns with the core board’s requirements.
   • Test the SYS_RESET* functionality thoroughly in both input and output modes during the development process.

7. Seek additional resources:

   • If further clarification is needed, consult NVIDIA’s official documentation or reach out to their developer support channels.
   • Join developer forums or communities focused on Jetson development for peer support and additional insights.

By following these guidelines and referring to the official Orin Nano Design Guide, developers can properly implement the SYS_RESET* pin functionality and ensure correct power sequencing in their custom carrier board designs for the Jetson Orin Nano.