External Reset and Power Loss Handling for Jetson Orin Nano Custom Carrier Board

Issue Overview

The discussion revolves around designing a custom carrier board for the Nvidia Jetson Orin Nano System-on-Module (SoM) with specific requirements for external reset functionality and power loss handling. The main challenges include:

• Implementing an external reset source controlled by a Master MCU
• Designing power supply and sequencing without using an MCU or power button
• Handling sudden power loss scenarios
• Understanding the correct usage of POWER_EN, SYS_RESET*, and SHUTDOWN_REQ* signals
• Determining voltage thresholds for the POWER_EN signal

The user seeks guidance on best practices and design considerations to ensure proper functionality and compliance with Nvidia’s requirements.

Possible Causes

1. Incorrect signal handling: Misunderstanding or misuse of POWER_EN, SYS_RESET*, and SHUTDOWN_REQ* signals can lead to improper reset or power-down behavior.

2. Non-compliance with design guidelines: Failing to follow Nvidia’s design requirements, especially regarding the SHUTDOWN_REQ* signal, may result in unreliable operation or potential damage to the SoM.

3. Inadequate power sequencing: Improper power supply design or sequencing without an MCU could lead to unstable operation or failure to boot.

4. Voltage threshold mismatch: Using incorrect voltage thresholds for the POWER_EN signal may cause unexpected behavior or failure to power on/off the SoM.

5. Insufficient protection against sudden power loss: Lack of proper handling for unexpected power loss scenarios could result in data corruption or system instability.

Troubleshooting Steps, Solutions & Fixes

1. Reference existing non-MCU designs:

   • Consult the ON/OFF logic design in the Nano carrier board P3449 schematic available in the Nvidia Developer Download Center (DLC) for a non-MCU design example.

2. Implement proper external reset mechanism:

   • Use SYS_RESET* as the external reset source, as mentioned in the Design Guide.
   • To reset the SoC and QSPI boot device without a full system power cycle, pull down SYS_RESET* against Ground using a MOSFET.

3. Handle POWER_EN signal correctly:

   • The VIH (High-level input voltage) of POWER_EN is approximately 3.85V.
   • Implement a voltage supervisor working with the limits VDD_IN = 5V ±5% according to the recommended operating conditions in the Orin Nano datasheet.

4. Ensure compliance with SHUTDOWN_REQ requirements*:

   • It is mandatory to service SHUTDOWN_REQ* to toggle POWER_EN from high to low, even in cases of sudden power loss.
   • The Orin SoM PMIC handles this internally with a supervisor at an undervoltage event (under 4.18V).

5. Implement proper power loss handling:

   • Design the carrier board to always service SHUTDOWN_REQ* before toggling POWER_EN, even in sudden power loss scenarios.
   • Consider implementing a power management IC or supervisor circuit to handle power sequencing and monitoring.

6. Use appropriate voltage thresholds:

   • Ensure that the voltage supervisor on the custom carrier board adheres to the recommended operating conditions for VDD_IN (5V ±5%).

7. Consult official documentation:

   • Thoroughly review the Jetson Orin Nano Design Guide and Datasheet for detailed specifications and requirements.
   • Pay special attention to sections related to power sequencing, reset mechanisms, and signal handling.

8. Consider alternative designs:

   • If possible, reconsider the use of an MCU for power supply and sequencing, as it may simplify the design and ensure compliance with Nvidia’s requirements.
   • Explore third-party reference designs or consult with Nvidia support for guidance on MCU-less designs.

9. Implement safeguards:

   • Design the carrier board with protection circuits to handle unexpected power fluctuations or loss.
   • Consider adding capacitors or a small battery backup to ensure proper shutdown sequences in case of sudden power loss.

10. Verify design compliance:

    • Before finalizing the design, thoroughly test the custom carrier board under various power and reset scenarios to ensure proper functionality and compliance with Nvidia’s requirements.
    • Pay particular attention to the behavior of SHUTDOWN_REQ*, POWER_EN, and SYS_RESET* signals during normal operation, reset, and power loss events.