PCIE_C7 Link Up Issues on Nvidia Jetson Orin Nano

Issue Overview

Users are experiencing difficulties with the PCIE_C7 interface on the Nvidia Jetson Orin Nano development board. The primary issue is that PCIE_C7 fails to link up under normal circumstances. However, when a jumper wire is used to pull up the PCIE2_RST pin, the link is successfully established. This problem affects the functionality of PCIe devices connected to the C7 interface and requires manual intervention (jumper wire) to work properly.

Key points:

• PCIE_C7 doesn’t link up by default
• Linking succeeds when PCIE2_RST is manually pulled up with a jumper wire
• The issue persists across different software configurations (JetPack 5.1.1, kernel 5.10)
• Another PCIe interface (PCIE_C1) works correctly due to hardware pull-up

Possible Causes

1. Hardware design issue: The PCIE_C7 reset pin (PCIE2_RST) lacks a default pull-up resistor in the hardware design, unlike PCIE_C1.

2. Pinmux configuration: Incorrect or suboptimal pin multiplexing settings in the device tree or kernel configuration.

3. Software initialization sequence: The PCIe controller might be initializing before the reset pin is properly configured.

4. Kernel driver issue: The PCIe driver may not be properly managing the reset signal for PCIE_C7.

5. Power sequencing problem: Improper power-up sequence for the PCIe interface could prevent proper initialization.

6. SFIO (Special Function I/O) misconfiguration: The PCIE2_RST pin may not be correctly set as an SFIO in the pinmux settings.

Troubleshooting Steps, Solutions & Fixes

1. Verify hardware design:

   • Review the schematic and compare PCIE_C7 and PCIE_C1 reset pin configurations.
   • Consider adding a pull-up resistor to the PCIE2_RST line if missing.

2. Check and modify pinmux settings:

   • Ensure PCIE2_RST (PIN_219) is configured as SFIO, not GPIO.
   • Modify the device tree file (tegra234-p3768-0000-a0.dtsi) to set the correct pinmux:

     pcie_c7_rst_pins: pcie-c7-rst-pins {
         nvidia,pins = "pex_l5_rst_n_pz1";
         nvidia,function = "pex";
         nvidia,pull = <TEGRA_PIN_PULL_UP>;
         nvidia,enable-input = <TEGRA_PIN_ENABLE>;
     };
     

3. Enable PCIe C7 in device tree:

   • Modify tegra234-p3768-0000-a0-pcie.dtsi to enable PCIe C7 in x1 mode:

     pcie@141a0000 {
         status = "okay";
         nvidia,max-speed = <3>;
         nvidia,num-lanes = <1>;
     };
     

4. Adjust PCIe initialization sequence:

   • If possible, modify the kernel driver to ensure the reset pin is configured before PCIe controller initialization.

5. Investigate software-based pull-up:

   • Attempt to control the reset pin through software by adding a GPIO driver:
     • Create a new file: kernel-5.10/drivers/gpio/gpio_reset.c
     • Modify kernel-5.10/drivers/gpio/Makefile to include the new driver
     • Implement logic to set the pin high before PCIe initialization

6. Try different pull settings:

   • In the pinmux configuration, change:

     nvidia,pull = <TEGRA_PIN_PULL_NONE>;
     

   to:

   nvidia,pull = <TEGRA_PIN_PULL_UP>;
   

7. Analyze dmesg output:

   • Compare dmesg outputs with and without the jumper wire to identify differences in initialization sequence or error messages.

8. Consult Nvidia documentation:

   • Review the Jetson Module Adaptation and Bring-Up guide, specifically the section on enabling PCIe in a customer CVB design:
     https://docs.nvidia.com/jetson/archives/r35.4.1/DeveloperGuide/text/HR/JetsonModuleAdaptationAndBringUp/JetsonAgxOrinSeries.html#enable-pcie-in-a-customer-cvb-design

9. Consider hardware workaround:

   • If software solutions fail, implement a more permanent hardware pull-up solution instead of using a jumper wire.

10. Seek Nvidia support:

    • If all else fails, contact Nvidia support with detailed logs, device tree modifications, and hardware design information for further assistance.

Note: Some of these steps may require advanced knowledge of kernel development and hardware design. Always backup your configurations before making changes, and be cautious when modifying kernel-level components.